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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
MC14519B 4-Bit AND/OR Selector or Quad 2-Channel Data Selector or Quad Exclusive NOR" Gate
The MC14519B is constructed with MOS P-channel and N-channel enhancement mode devices in a monolithic structure. These complementary MOS logic gates find primary use where low power dissipation and/or high noise immunity is desired. This device provides three functions in one package; a 4-Bit AND/OR Selector, a Quad 2-Channel Data Selector, or a Quad Exclusive NOR Gate. * Diode Protection on All Inputs * Supply Voltage Range = 3.0 Vdc to 18 Vdc * Capable of Driving Two Low-power TTL Loads or One Low-power Schottky TTL Load Over the Rated Temperature Range * Plug-in Replacement for CD4019 in Most Applications
L SUFFIX CERAMIC CASE 620
P SUFFIX PLASTIC CASE 648
D SUFFIX SOIC CASE 751B
ORDERING INFORMATION
MC14XXXBCP MC14XXXBCL MC14XXXBD Plastic Ceramic SOIC
LOGIC DIAGRAM
CONTROL INPUTS A B X0 Y0 X1 DATA INPUTS Y1 X2 Y2 9 14 6 7 4 5 2 3 13 Z3 12 Z2 11 Z1 10 Z0
TA = - 55 to 125C for all packages.
TRUTH TABLE
Control Inputs A 0 0 1 1 B 0 1 0 1 Output Zn 0 Yn Xn xn Yn
NOTE: Xn Yn means Xn (Exclusive-NOR) Yn
X3 15 Y3 1 VDD = PIN 16 VSS = PIN 8
REV 3 1/94
(c)MOTOROLA CMOS LOGIC DATA Motorola, Inc. 1995
MC14519B 1
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII
MAXIMUM RATINGS* (Voltages Referenced to VSS)
Symbol VDD Parameter DC Supply Voltage Value Unit V V - 0.5 to + 18.0 Vin, Vout Iin, Iout PD Tstg TL Input or Output Voltage (DC or Transient) - 0.5 to VDD + 0.5 10 500 - 65 to + 150 260 Input or Output Current (DC or Transient), per Pin Power Dissipation, per Package Storage Temperature Lead Temperature (8-Second Soldering) mA mW
PIN ASSIGNMENT
Y3 X2 Y2 X1 Y1 X0 Y0 VSS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD X3 B Z3 Z2 Z1 Z0 A
_C _C
* Maximum Ratings are those values beyond which damage to the device may occur. Temperature Derating: Plastic "P and D/DW" Packages: - 7.0 mW/_C From 65_C To 125_C Ceramic "L" Packages: - 12 mW/_C From 100_C To 125_C
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Characteristic Symbol VOL VDD Vdc 5.0 10 15 5.0 10 15 5.0 10 15 VIH 5.0 10 15 IOH Source 5.0 5.0 10 15 IOL 5.0 10 15 15 -- 5.0 10 15 5.0 10 15 - 3.0 - 0.64 - 1.6 - 4.2 0.64 1.6 4.2 -- -- -- -- -- 3.5 7.0 11 Min -- -- --
- 55_C
25_C
125_C
Max
Min -- -- --
Typ # 0 0 0
Max
Min -- -- --
Max
Unit Vdc
Output Voltage Vin = VDD or 0
"0" Level
0.05 0.05 0.05 -- -- -- 1.5 3.0 4.0 -- -- -- -- -- -- -- -- -- --
0.05 0.05 0.05 -- -- -- 1.5 3.0 4.0 -- -- -- -- -- -- -- -- -- --
0.05 0.05 0.05 -- -- -- 1.5 3.0 4.0
"1" Level Vin = 0 or VDD Input Voltage "0" Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) "1" Level (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Input Current Input Capacitance (Vin = 0) Quiescent Current (Per Package) Total Supply Current** (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching)
VOH
4.95 9.95 14.95 -- -- --
4.95 9.95 14.95 -- -- -- 3.5 7.0 11 - 2.4 - 0.51 - 1.3 - 3.4 0.51 1.3 3.4 -- -- -- -- --
5.0 10 15 2.25 4.50 6.75 2.75 5.50 8.25 - 4.2 - 0.88 - 2.25 - 8.8 0.88 2.25 8.8 0.00001 5.0 0.005 0.010 0.015
4.95 9.95 14.95 -- -- -- 3.5 7.0 11 - 1.7 - 0.36 - 0.9 - 2.4 0.36 0.9 2.4 -- -- -- -- --
Vdc
VIL
Vdc
Vdc -- -- -- mAdc -- -- -- -- -- -- -- 1.0 -- 150 300 600 mAdc
Sink
Iin Cin IDD
0.1 -- 5.0 10 20
0.1 7.5 5.0 10 20
Adc pF Adc
IT
IT = (1.2 A/kHz) f + IDD IT = (2.4 A/kHz) f + IDD IT = (3.6 A/kHz) f + IDD
Adc
#Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. ** The formulas given are for the typical characteristics only at 25_C. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL - 50) Vfk where: IT is in A (per package), CL in pF, V = (VDD - VSS) in volts, f in kHz is input frequency, and k = 0.004.
MC14519B 2
MOTOROLA CMOS LOGIC DATA
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)
Characteristic Output Rise and Fall Time tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns Propagation Delay Time tPLH, tPHL = (1.7 ns/pF) CL + 165 ns tPLH, tPHL = (0.66 ns/pF) CL + 82 tPLH, tPHL = (0.5 ns/pF) CL + 65 ns Symbol tTLH, tTHL VDD 5.0 10 15 5.0 10 15 Min -- -- -- -- -- -- Typ # 100 50 40 250 115 90 Max 200 100 80 500 225 165 Unit ns tPLH, tPHL ns * The formulas given are for the typical characteristics only at 25_C. #Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. +VDD VDD PULSE GENERATOR Vin A B X0 Y0 X1 Y1 X2 Y2 X3 Y3 VSS Z3 CL Z2 CL Z1 CL Vin 90% 10% 50% DUTY CYCLE Z0 CL 20 ns 20 ns VDD VSS ISS 500 F
Figure 1. Dynamic Power Dissipation Test Circuit and Waveform
VDD 20 ns PULSE GENERATOR V A DD Z0 B X0 Z1 Y0 X1 Y1 Z2 X2 Y2 X3 Y3 V Z3 SS CL CL OUTPUTS CL tPLH CL OUTPUT 50% VOL OUTPUT INPUT tPHL 90% 50% 10% tTHL tTLH tPHL VOH 90% 50% 10% tPLH 20 ns VDD VSS VOH VOL
Figure 2. Switching Time Test Circuit and Waveforms
MOTOROLA CMOS LOGIC DATA
MC14519B 3
TYPICAL CIRCUIT APPLICATIONS
DATA REGISTER SELECTION COMPARISON
DATA A CLOCK A RESET A
4-BIT REGISTER A Q1 Q2 Q3 Q4
MC14015B DUAL 4-BIT REGISTER
4-BIT REGISTER B Q1 Q2 Q3 Q4
DATA B CLOCK B RESET B
CONTROL A CONTROL B
A B
X0
X1
Z0
X3 Y0 Y1 Y2 MC14519B AND/OR SELECT/EXCL NOR Z1 Z2
X2
Y3
Z3
INVERT MC14070B QUAD EXCLUSIVE OR
Q0
Q1
Q2
Q3
CONVERSION TABLE
Operation Code A 0 0 1 1 0 0 1 1 B 0 0 0 0 1 1 1 1 INV 0 1 0 1 0 1 0 1 Q0 0 1 X0 X0 Y0 Y0 X0 X0 Y0 Y0 X1 X1 Q1 0 1 X1 X1 Y1 Y1 Y1 Y1 X2 X2 Output Q2 0 1 X2 X2 Y2 Y2 Y2 Y2 X3 X3 Q3 0 1 X3 X3 Y3 Y3 Y3 Y3 Function Inhibit, all zeros Inhibit, all ones Control A Control A and Invert Control B Control B and Invert Exclusive NOR Exclusive OR
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.
MC14519B 4
MOTOROLA CMOS LOGIC DATA
OUTLINE DIMENSIONS
L SUFFIX CERAMIC DIP PACKAGE CASE 620-10 ISSUE V
-A-
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. DIM A B C D E F G H K L M N INCHES MIN MAX 0.750 0.785 0.240 0.295 --- 0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 --- 5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0_ 15 _ 0.51 1.01
-B-
1 8
C
L
-T-
SEATING PLANE
N E F D G
16 PL
K M J
16 PL
0.25 (0.010)
M
M
TB
S
0.25 (0.010)
TA
S
P SUFFIX PLASTIC DIP PACKAGE CASE 648-08 ISSUE R
-A-
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01
B
1 8
F S
C
L
-T- H G D
16 PL
SEATING PLANE
K
J TA
M
M
0.25 (0.010)
M
MOTOROLA CMOS LOGIC DATA
MC14519B 5
OUTLINE DIMENSIONS
D SUFFIX PLASTIC SOIC PACKAGE CASE 751B-05 ISSUE J
-A-
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019
16
9
-B-
1 8
P
8 PL
0.25 (0.010)
M
B
S
G F
K C -T-
SEATING PLANE
R
X 45 _
M D
16 PL M
J
0.25 (0.010)
TB
S
A
S
DIM A B C D F G J K M P R
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MC14519B 6
*MC14519B/D*
MOTOROLA CMOS LOGIC DATA MC14519B/D

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